`timescale 1ns / 1ps

module reg8file (
    input clk,
    input clrn,
    input wen,
    input [7:0] d,
    input [2:0] wsel,
    input [2:0] rsel,
    output reg [7:0] q
);
    wire [7:0] r0, r1, r2, r3, r4, r5, r6, r7;
    reg [7:0] we_n;

    reg8 file0(clk, clrn, d, we_n[0], r0);
    reg8 file1(clk, clrn, d, we_n[1], r1);
    reg8 file2(clk, clrn, d, we_n[2], r2);
    reg8 file3(clk, clrn, d, we_n[3], r3);
    reg8 file4(clk, clrn, d, we_n[4], r4);
    reg8 file5(clk, clrn, d, we_n[5], r5);
    reg8 file6(clk, clrn, d, we_n[6], r6);
    reg8 file7(clk, clrn, d, we_n[7], r7);

    always@(wsel, wen) begin
        we_n = 8'b1111_1111;
        if (~wen) begin
            case(wsel)
                3'b000: we_n[0] = 1'b0;
                3'b001: we_n[1] = 1'b0;
                3'b010: we_n[2] = 1'b0;
                3'b011: we_n[3] = 1'b0;
                3'b100: we_n[4] = 1'b0;
                3'b101: we_n[5] = 1'b0;
                3'b110: we_n[6] = 1'b0;
                3'b111: we_n[7] = 1'b0;
            endcase
        end else begin
            we_n = 8'b1111_1111;
        end
    end
        
    always@(rsel, r0, r1, r2, r3, r4, r5, r6, r7) begin
        case(rsel)
            3'b000: q = r0;
            3'b001: q = r1;
            3'b010: q = r2;
            3'b011: q = r3;
            3'b100: q = r4;
            3'b101: q = r5;
            3'b110: q = r6;
            3'b111: q = r7;
        endcase
    end
endmodule
